Analog-to-Digital Conversion


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This approach has been widely adopted in many communication systems for wideband spectrum applications, since the converters can work at lower speeds without sacrificing the overall system performance. It results in a periodic spectrum with a period equal to the sampling rate [ 25 ]. In practice, however, there are deviations from the ideal behavior that are caused by the mismatches between the individual ADCs.

A brief review of all of them is included in the subsequent sections. Clock timing errors occur when the digitization clocks of the individual ADCs are not appropriately synchronized. As a result, the input signal x t is sampled in such a way that the sampling time instances are not necessarily uniformly spaced in time. Errors may be systematic skew or random jitter. Taking this factor into account, Eq. It can be noticed that, in contrast with the ideal case, the spectrum is repeated in Eq. In other words, spurious replica spectra called image spurs will appear at.

The analysis is similar as for timing errors.

Introduction to ADC and DAC

Gain errors also produce image spurs at. A formula for the SNDR, taking into account the contribution of gain and offset errors, will be given a few lines below. The offsets of each ADC may be also different and then, as with the gain mismatch case, even a DC input may produce different outputs. Offset errors cause noise peaks offset spurs at. The input signal is a sinusoid at a frequency of 2. In practice, clock timing errors are the most critical gains and offsets can be calibrated more easily.

Several approaches have been proposed to deal with mismatches between individual ADCs. Some of the most relevant are presented in the subsequent section.

ADC and DAC

To implement interleaving systems, several approaches, which differ in the calibration method and in the intended application, are possible. This section begins with a brief summary of the most prevalent calibration methods, discussing their advantages and disadvantages. Then, a review of several approaches for designing SDR, ultra wideband UWB , and multistandard systems will be presented. The first one consists of reducing the electrical and physical differences between the channels.

The gain is typically controlled using a common reference voltage and carefully designing the layouts. Phase matching is achieved by ensuring that all the clock paths are as similar in length as possible. Nevertheless, unlike approaches based on digital processing, these techniques are not well suited for implementations based on COTS Commercial Off The Shelf , which is very convenient for SDR designs due to its flexibility and ease of programming. Digital processing techniques have several advantages, including technology scaling, flexibility, the ease of portability to the next technologies generation, a low power consumption, and the possibility of being implemented through a cheap CMOS process.

Moreover, digital techniques are more efficient for the compensation of timing skews than analog techniques, due to the fact that they are more stable with the temperature and the wide bandwidths used in SDR applications. In spite of the previously stated digital processing advantages, analog calibration techniques have benefits as well.

Successive Approximation Conversion

For example, one advantage of analog offset calibration is that the correction values do not suffer from quantization [ 29 ]. Thus, the ADC offset can be corrected to less than one LSB without adding the extra bits needed when the offset correction is performed in the digital domain [ 30 ]. Offline calibration requires less circuitry, but interrupts the normal operation of the ADC. It is usually applied when the parameters of the circuit do not vary much with environmental parameters e.

On the other hand, background techniques enable continuous calibration, with the ADC running in normal operation, and are suitable to be used when disconnecting the ADC is not an option [ 34 ]. A particularly appealing background approach is the one based on randomization [ 32 ]. In this approach, the ADC channel is selected randomly for each sampling instant. This can be performed using a digital circuit thus avoiding the need for new analog circuitry , which constitutes the main benefit of this approach.

Next, only B can be selected and so on. Therefore, to enable the randomization process, one or more extra ADCs i. In this way, there always exist at least two available ADCs at each sampling time.

20.2 Basic Operation

Although this structure implies an additional hardware cost, Dyer et al. The sequence of randomly chosen ADCs is shown at the top of the figure. Apart from the use in randomization techniques, an extra ADC might be employed in other background approaches. Doris et al. When the calibration cycle is finished, another ADC is selected for calibration, being replaced in the conversion mode by the previously calibrated ADC.

From Analog to Digital – Part 2: The Conversion Process | Nutaq | Nutaq

The calibration of these ADCs is performed using another ADC as a reference, in order to match gain and offset with it. Therefore, an analog calibration is implemented. However, the main drawbacks are the noise introduced by the additional analog circuitry, and the degradation in speed when extra ADCs are used to substitute the ADC under calibration [ 36 ]. Moreover, there are also calibration techniques specifically devised either for static i. A common alternative to reduce the cost of the extra circuitry due to the added DACs is to implement the gain and offset calibrations after a FFT fast Fourier transform evaluation, via software, achieving the compensation from the study of the output spectrum [ 38 ].

An additional benefit of this technique is to take the advantage of the repetition and symmetry properties of the FFT [ 39 ]. On the other hand, clock skew errors are difficult to correct and lead to more stringent limitations on interleaved architectures [ 40 ], especially for SDR and UWB applications as explained in Ref.

Moreover, the aperture delay strongly depends on the temperature. As a consequence, there are many unknown factors affecting these timing mismatches that make the estimation of the spurious component level even harder. Some traditional ideas for correcting the skew errors are to add programmable delay lines or to implement a signal postprocessing. Dyer et al. Another specific technique for timing errors correction is the one based on polyphase digital filter blocks [ 41 ], which can be easily implemented using an FPGA and, therefore, results highly suitable for SDR applications based on COTS.

The filter structures used to calibrate these dynamic errors are designed as a function of the number of channels i. Reference [ 41 ] gives the ratio R between the number of channels M and the number of necessary filters N , this ratio being lower when the number of channels is increased. As a consequence, for a high number of ADCs this method is not efficient. Lastly, an additional drawback of this method is that conventional filters do not have enough resolution to tune the group delay in the highest frequency systems, where the calibration precisely has to be more accurate [ 43 ].

Thus, designing these filters is an important challenge in their own. Many research works have been published in order to implement receivers and ADC systems based on interleaving techniques, most of them with application in SDR.

The Analog World

Some of these systems are implemented in IC, whereas others are implemented with COTS, leading to some benefits for SDR applications, such as significant time and cost savings compared with developing an integrated circuit. Moreover, this solution means a reasonable tradeoff between cost and complexity.


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The proposed system presented in Ref. For instance, Tamba et al. These definitions, however, are somewhat arbitrary and largely reflect the current state-of-the-art. Within these broad categories, ADCs may also be grouped according to converter architecture. The most popular types are flash, pipelined, successive approximation- register, and sigma-delta. Each architecture offers certain advantages with respect to conversion speed, accuracy, and other parameters. The characteristics associated with each architecture help determine its suitability for a given application.

Over time, the migration of ADC designs to CMOS processes with smaller geometries has increased the possibilities for performance enhancements, while also allowing higher levels of integration. That integration can increase the number of conversion channels achieved on a single die, or allow conversion- related functions to be brought on-chip. As a result, die size and, consequently, package size depend on the semiconductor process employed. The process also determines supply voltage, which along with conversion speed, influences power dissipation.

In the flash or parallel ADC architecture, an array of 2N-1 comparators converts an analog signal to digital with a resolution of N bits.

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